From fec760a3c094102487043a7a4562fb1b5c7b75a3 Mon Sep 17 00:00:00 2001 From: "Claude (sandbox)" Date: Mon, 13 Jul 2026 09:48:24 +0000 Subject: [PATCH] docs(causal): record the reserve-shortfall verdict in the demo header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Occupancy probe on 24 cores: δ = 0.3µs/item (0.1% of the serialized path); wide guard leaves the @50% cell unchanged. The +84-vs-+100 shortfall is controller-side (injected 327ms of the ideal 350ms over the 700ms window, plus ~3% real-rate dip during experiments), not unguarded stage time. urus's ~70µs/request remainder remains the guard-placement case; the occupancy probe discriminates the two. --- examples/causal_pipeline.rs | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/examples/causal_pipeline.rs b/examples/causal_pipeline.rs index b06db8b..f50ae5f 100644 --- a/examples/causal_pipeline.rs +++ b/examples/causal_pipeline.rs @@ -30,6 +30,16 @@ //! at baseline and reports the unguarded per-item //! overhead δ plus the impact ceiling it implies. //! +//! Result (24-core run, 2026-07-13, job f9305cbb): δ measured 0.3µs/item — +//! 0.1% of the serialized path — and `wide` does not move the @50% cell +//! (+83.5/+86.3 vs work's +81.5/+86.7). This demo's +84-vs-+100 @50% +//! shortfall is therefore NOT unguarded stage time; it is controller-side: +//! injected delay reaches ~327ms of the ideal 350ms over the 700ms window, +//! plus a ~3% real-throughput dip while experiments run. Contrast urus's +//! causal_bench, where the same arithmetic identified a real ~70µs/request +//! unguarded remainder (recv/reply outside the store guard). Sites measure +//! what they wrap — and the occupancy probe tells you which case you're in. +//! //! Prints a summary, writes `profile.coz` (Coz plot-compatible), and — given //! enough cores for the pipeline to actually run in parallel — checks the //! expected separation and exits nonzero if it doesn't hold, so a CI box can