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fix bug in test that only shows on multicore enviroments

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smarm
2026-06-12 00:05:55 +02:00
parent 156dcca496
commit cc4000a165
1 changed files with 16 additions and 14 deletions
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tests/select.rs
+16 -14
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@@ -6,22 +6,22 @@
use smarm::{channel, run, select, spawn}; use smarm::{channel, run, select, spawn};
use std::sync::atomic::{AtomicI64, Ordering}; use std::sync::atomic::{AtomicI64, Ordering};
use std::sync::Arc;
use std::time::{Duration, Instant}; use std::time::{Duration, Instant};
static OUT: AtomicI64 = AtomicI64::new(0);
#[test] #[test]
fn ready_arm_returns_immediately_without_parking() { fn ready_arm_returns_immediately_without_parking() {
OUT.store(0, Ordering::SeqCst); let out = Arc::new(AtomicI64::new(0));
run(|| { let out2 = out.clone();
run(move || {
let (txa, rxa) = channel::<i64>(); let (txa, rxa) = channel::<i64>();
let (_txb, rxb) = channel::<i64>(); let (_txb, rxb) = channel::<i64>();
txa.send(42).unwrap(); txa.send(42).unwrap();
let i = select(&[&rxb, &rxa]); let i = select(&[&rxb, &rxa]);
assert_eq!(i, 1); assert_eq!(i, 1);
OUT.store(rxa.try_recv().unwrap().expect("ready arm must hold a message"), Ordering::SeqCst); out2.store(rxa.try_recv().unwrap().expect("ready arm must hold a message"), Ordering::SeqCst);
}); });
assert_eq!(OUT.load(Ordering::SeqCst), 42); assert_eq!(out.load(Ordering::SeqCst), 42);
} }
#[test] #[test]
@@ -39,8 +39,9 @@ fn lower_index_wins_when_several_arms_are_ready() {
#[test] #[test]
fn parks_until_any_arm_fires() { fn parks_until_any_arm_fires() {
OUT.store(0, Ordering::SeqCst); let out = Arc::new(AtomicI64::new(0));
run(|| { let out2 = out.clone();
run(move || {
let (txa, _rxa_keepalive) = (channel::<i64>().0, ()); let (txa, _rxa_keepalive) = (channel::<i64>().0, ());
let _hold = txa; // arm a: sender alive, never sends let _hold = txa; // arm a: sender alive, never sends
let (txa, rxa) = channel::<i64>(); let (txa, rxa) = channel::<i64>();
@@ -52,10 +53,10 @@ fn parks_until_any_arm_fires() {
}); });
let i = select(&[&rxa, &rxb]); let i = select(&[&rxa, &rxb]);
assert_eq!(i, 1); assert_eq!(i, 1);
OUT.store(rxb.try_recv().unwrap().unwrap(), Ordering::SeqCst); out2.store(rxb.try_recv().unwrap().unwrap(), Ordering::SeqCst);
h.join().unwrap(); h.join().unwrap();
}); });
assert_eq!(OUT.load(Ordering::SeqCst), 7); assert_eq!(out.load(Ordering::SeqCst), 7);
} }
#[test] #[test]
@@ -164,8 +165,9 @@ fn select_then_plain_recv_on_a_loser_arm() {
#[test] #[test]
fn select_loop_drains_two_producers_completely() { fn select_loop_drains_two_producers_completely() {
const N: i64 = 200; const N: i64 = 200;
OUT.store(0, Ordering::SeqCst); let out = Arc::new(AtomicI64::new(0));
run(|| { let out2 = out.clone();
run(move || {
let (txa, rxa) = channel::<i64>(); let (txa, rxa) = channel::<i64>();
let (txb, rxb) = channel::<i64>(); let (txb, rxb) = channel::<i64>();
let ha = spawn(move || { let ha = spawn(move || {
@@ -204,11 +206,11 @@ fn select_loop_drains_two_producers_completely() {
Err(_) => break, Err(_) => break,
} }
} }
OUT.store(sum, Ordering::SeqCst); out2.store(sum, Ordering::SeqCst);
ha.join().unwrap(); ha.join().unwrap();
hb.join().unwrap(); hb.join().unwrap();
}); });
assert_eq!(OUT.load(Ordering::SeqCst), 2 * (0..200i64).sum::<i64>()); assert_eq!(out.load(Ordering::SeqCst), 2 * (0..200i64).sum::<i64>());
} }
#[test] #[test]